Job Description:
Verify a block or functional feature and lead it to closure. Write scalable and re-usable testbenches from scratch, using the framework of the verification methodology. Create test cases, functional coverage models and bring the verification to closure. Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Be involved in documenting verification strategy including test plans, verification micro-architecture, coverage objects etc.
Mandatory Requirements:
- More than a decade of experience writing and debugging test benches.
- Must have deep understand of full ASIC cycle, right from conceptualization to TapeOut.
- Must have proficiency in constrained random verification methodologies like UVM/VMM/OVM.
- Must be proficient with System Verilog.
- Should have exceptionally good command over fundamental OOP principles.
- A good understanding of a complex protocol like PCIe or other multi-layered protocol.
- Should be open to learning verification methodologies and strategies, that may be cutting edge and different from the industry standard.
- Should be motivated and be open to mentoring the team.
These Requirements are a plus:
- Scripting knowledge of Python or Perl.
- Reasonably comfortable with Makefiles.
- Experience with verifying other peripheral protocols like AXI.