Location: Austin,TX, USA
- Local to Austin Market - No H1B candidate - Top 2 candidates per suppliers Key Responsibilities Include: • Drive the timely development and debug of new features on the custom memory controller. • Working on SOC IP delivery with all sanity checks. • Work on timing debug and closure. • Working on LINT, CDC flows and analysis. • Work with the verification team to verify the functionality and correctness of the design. • Collaborate with implementation to achieve your timing and area. • Produce quality RTL on schedule meeting PPA goals Requirements Skills And Qualifications • Knowledge of Verilog, scripting, STA. • Knowledge of memory controller. • Knowledge of PHY design. • Experience in one or more memory technologies: DDR4/5, LPDDR & HBM. • Experience with a scripting language like Perl or Python. • Energetic, curiosity, and passion in logic design. • Good written and verbal communication skills. • Efficient digital design techniques. • Knowledge of JEDEC memory standards.