Opening: Physical Design STA Location: Irvine, CA Duration: Long Term We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
Responsibilities - Develop/support automated block and full chip level advanced timing/noise signoff flows (with advanced and parametric on chip variation, and voltage drop aware STA)
- Define block and full chip timing signoff criterion, methodology, constraints, modes and scenarios and close timing at multi-corner and multi-mode environments
- Develop/support signoff STA timing/power optimization engineering change order flows (Timing ECOs) and integrate them into physical design flow
- Work with systems and architecture, SOC integration, verification, DFT, mixed signal, IP owners, synthesis, and place/route teams to address the design challenges in the context of timing sign-off
- Generate block timing budgets, clock and I/O context files
- Debug and drive fixing of constraint correlation issues between top and block level
- Develop clock network simulation and jitter analysis methodologies
Basic Qualifications - Bachelor's degree in electrical engineering, computer engineering or computer science
- Experience in static timing analysis and/or timing closure of high-performance SOC designs
Preferred Skills And Experience - Full chip and block level STA tapeout experience, constraint generation and partitioning
- Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations, voltage drop aware STA, and CRPR
- Experience with memories, I/Os, Analog IPs, SerDes, DDR, etc. preferred
- Experience in industry standard STA and Noise/Signal integrity analysis tools
- Experience in clock jitter simulation and analysis methodologies
- Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on physical design and timing closure
- Familiar with ASIC synthesis and physical design flows and methodologies
- Experience with high reliability design and implementations
- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.)
- Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
Additional Requirements - Must be willing to travel when needed (typically
- Willing to work extended hours and weekends to meet critical deadlines, as needed