Responsibilities
Our team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs.
- Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM.
- Develop tests using UVM or C/C++
- Analyse and debug test failures with designers to deliver functionally correct design.
Qualifications
- 8 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP's
- Knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
- Good understanding of computer architecture
- Scripting language such as Python or Perl