Location: Austin,TX, USA
Responsible for methodology, flow development and execution for Design Verification (DV) of complex digital, mixed-signal IP and ARM CPU subsystems. Develop and deploy new DV methodologies. Develop DV test plan based on the specification, come up with appropriate DV strategy, build test benches/infrastructure, develop test cases to verify the design using simulation tools. Responsible to debug any RTL/GLS/Silicon failures and work with RTL engineers to get the bugs fixed #LI-NOPOST
Required: - BS or MS degree in Computer Engineering or Electrical/Electronic Engineering - 7+ Years of experience in Design Verification (DV) of Complex IP, CPU Systems and/or SoC - Experienced in latest DV methodologies: Formal Verification, System Verilog and UVM, Assembly/C-based Verification, Mixed-signal IP Verification, AMS - Proven ability to develop and deploy new DV methodologies - Experienced in developing a DV plan based on Functional Specification, build the necessary test bench/infrastructure, develop tests and verify design - Strong debugging skills and familiar with using industry standard simulation (e.g.: VCS) and debug tools - Strong scripting skills Plus: - ARM CPU knowledge and DV experience - Mixed Signal IP Verification